Dynamic Processor Throttling for Power Efficient Computations

We propose a novel hardware-based DVS technique called dynamic processor throttling (DPT) for power efficient computations. DPT focuses on performance balance between processor and main memory. When performance imbalance is detected, DPT tries to redresses the imbalance by setting clock frequency and supply voltage of processor to a well-balanced point. This paper describes the micro-architecture mechanisms of DPT and shows evaluation results on energy saving and performance compared with a conventional cache-miss driven DVS technique. The results reveal that DPT can reduce 17% of energy with 3.4% performance degradation and DPT surpasses the conventional technique in both performance and energy perspective.